Manufacturers of memory and integrated circuits have established a number of standardized communication protocols for memory devices to communicate with the integrated circuits over a multiplexed bus. Many memory devices include logic circuits that conform to these standardized communication protocols. These logic circuits may be configured to provide logic functions for decoding signals from the integrated circuit and provide memory access. The integrated circuit typically communicates with the memory device over a bus. The bus width (e.g., the number of separate signal channels) may be limited by the physical size and layout of the memory device and/or integrated circuit.
FIG. 1 is a block diagram illustrating a typical prior art circuit system 100. The prior art circuit system 100 includes an integrated circuit 102, a memory device 104, and a bus 114 of width “n” configured to communicate signals, using the “n” conductors, between the integrated circuit 102 and the memory device 104.
The integrated circuit 102 includes an application logic 106, configured for the integrated circuit 102 to operate as a microprocessor, an application specific integrated circuit (ASIC), a peripheral interface, or the like. The integrated circuit 102 further includes a communications protocol logic 108 configured to provide communication between the integrated circuit 102 and the memory device 104 according to a standard communications protocol.
In various embodiments, the memory device 104 includes static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), non-volatile random access memory (NVRAM), read only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable PROM (EEPROM), double data rate synchronous DRAM (DDRAM), embedded DRAM (EDRAM), flash memory, disk drives, or the like. In some embodiments, memory device 104 includes a memory interface logic 110 and a memory array 112. In some embodiments, the memory array 112 comprises an array of memory elements such as memory cells. The memory interface logic 110 is configured to receive signals from the communications protocol logic 108 according to the standard communications protocol and provide memory access to the memory array 112. Memory access includes writing data to the memory, reading data from the memory, performing error detection and/or correction, resetting the memory, testing the memory, and the like.